The 8514/A driver also uses a data structure to hold register values that will be written to the hardware. In the XGA driver, this structure was called ShadowXGARegs. In the 8514/A driver, it is called the Shadow8514Regs structure. The definition for the Shadow8514Regs is located in the XGAADAPT.H file.
typedef struct _MM8514Reg
{
/**********************************************************************/
/* DRAWING CONTROL REGISTERS */
/**********************************************************************/
/**************************************************************/
/* X0 and Y0 are the current position values used as the */
/* starting point for all drawing operations. Most of the */
/* drawing ops update this point during executions. Any */
/* attempt to read these values while drawing could result */
/* in meaningless data. */
/**************************************************************/
volatile USHORT X0; /* 86e8 r/w */
volatile USHORT Y0; /* 82e8 r/w */
/**************************************************************/
/* The following two registers are dual purpose registers */
/* that are used for both Line drawing and BitBlt. */
/* */
/* When used during a Blt, X1 and Y1 specify the target */
/* rectangle coordinates. */
/* */
/* When used during a Line drawing op, K1 and K2 specify the */
/* axial step constant and the diagonal step constant, */
/* respectively. These values can be calculated as follows: */
/* */
/* K1 = 2 * (minor axis delta) */
/* K2 = [2 * (minor axis delta)] */
/* [2 * (major axis delta)] */
/**************************************************************/
volatile USHORT X1; /* 8ee8 w */
volatile USHORT Y1; /* 8ae8 w */
volatile USHORT K1; /* 8ae8 w */
volatile USHORT K2; /* 8ee8 w */
/*********************************************************************/
/* Error Term is used during line drawing. The error term */
/* is calculated as: */
/* */ */
/* Err_Term = [2 * (minor axis delta)]
/* (major axis delta) - fixup */
/*********************************************************************/
volatile USHORT Err_Term; /* 92e8 r/w */
/*********************************************************************/
/* Note : LY, the counter part to LX, is accessed through Index 0 */
/* of the Multifunction Control Register, BEE8. */
/*********************************************************************/
volatile USHORT LX; /* 96e8 w */
/*********************************************************************/
/* These two registers are used to pass commands to the Display */
/* Processor and to check the status of the command queue. */
/* */
/* Commands that can be initiated are: */
/* */
/* 000 No Operation Performed */
/* 001 Line Draw */
/* 010 Fast-Fill Rectangle */
/* 011 Fill Rectangle Vertically (#1) */
/* 100 Fill Rectangle Vertically (#2) */
/* 101 Draw Line for Area Fill */
/* 110 Copy Rectangle */
/* 111 reserved */
/* */
/* Before initiating a command, all of the attributes registers */
/* necessary for the primitive should be set up first. */
/* */
/* The QStatus register indicates whether or not a command is */
/* currently being executed and how many of the eight slots in the */
/* queue are currently used. */
/* */
/* Queue State Value Meaning */
/* ----------------- ------- */
/* 00000000 Queue Empty */
/* 00000001 7 Entries available */
/* 00000011 6 Entries available */
/* 00000111 5 Entries available */
/* 00001111 4 Entries available */
/* 00011111 3 Entries available */
/* 00111111 2 Entries available */
/* 01111111 1 Entries available */
/* 11111111 Queue Full */
/*********************************************************************/
volatile CMDFLAG Cmd_Flags; /* 9ae8 w */
volatile QSTATUS QStatus; /* 9ae8 r */
/*********************************************************************/
/* Attribute Registers */
/*********************************************************************/
volatile SSTROKE ShortStroke; /* 9ee8 w */
#ifndef BPP24
volatile USHORT Color_0; /* a2e8 w */
volatile USHORT Color_1; /* a6e8 w */
volatile USHORT Write_Enable; /* aae8 w */
volatile USHORT Read_Enable; /* aee8 w */
volatile USHORT Color_Comp; /* b2e8 w */
#else
volatile ULONG Color_0; /* a2e8 w */
volatile ULONG Color_1; /* a6e8 w */
volatile ULONG Write_Enable; /* aae8 w */
volatile ULONG Read_Enable; /* aee8 w */
volatile ULONG Color_Comp; /* b2e8 w */
#endif
volatile MIX Function_0; /* b6e8 w */
volatile MIX Function_1; /* bae8 w */
/*********************************************************************/
/* The register at BEE8 is a multifunction control register for */
/* drawing operations. The different functions are differentiated */
/* by an index value in the high four bits. */
/*********************************************************************/
volatile USHORT LY; /* bee8 w Index 0 */
volatile USHORT YMin; /* bee8 w Index 1 */
volatile USHORT XMin; /* bee8 w Index 2 */
volatile USHORT YMax; /* bee8 w Index 3 */
volatile USHORT XMax; /* bee8 w Index 4 */
volatile USHORT Config; /* bee8 w Index 5 */
volatile USHORT Pattern_0; /* bee8 w Index 8 */
volatile USHORT Pattern_1; /* bee8 w Index 9 */
volatile PIXMODE Mode; /* bee8 w Index A */
/*********************************************************************/
/* Color_0_Wait is the only mechanism for moving data to and from */
/* the 8514's VRAM. The register is capable of dealing with Pixel */
/* mode and Planar mode color data. The type used is determined by */
/* Config version of the Multifunction Control Register, BEE8. */
/*********************************************************************/
volatile USHORT Color_0_Wait; /* e2e8 r/w */
/*********************************************************************/
/* When read, this register is used to query information about the */
/* graphics processor. Information available is whether or not... */
/* */
/* 1.) The graphics processor is idle. */
/* 2.) A command was written to a full queue. */
/* 3.) The Color_0_Wait register was read without any data being */
/* available to read. */
/* 4.) A write to a pixel within the clipping rectangle is about */
/* to be made. */
/* */
/* When written to, this register is used to enable and/or reset */
/* any of the above registers.
/*********************************************************************/
// volatile STATCTL Control; /* 42e8 w */
// volatile STATCTL Status; /* 42e8 r */
volatile USHORT Control; /* 42e8 w */
volatile USHORT Status; /* 42e8 r */
/*********************************************************************/
/* The register selects which 4KB page of the 32KB ROM */
/* on-board the IBM 8514/A is mapped to memory. This only applies */
/* to IBM* Micro Channel* computers that use the power-on self test. */
/* We should be able to ignore this register for other computers. */
/* However, we must be careful not to cause a conflict with VGA ROMs.*/
/*********************************************************************/
volatile USHORT Prom_Page; /* 46e8 w */
/*********************************************************************/
/* These two main purposes of this register are to set the clock */
/* speed, 25.175 MHz or 44.9 MHz, and to enable or disable the */
/* VGA pass-thru feature of the 8514/A. */
/*********************************************************************/
volatile MISCIO Misc_IO; /* 4ae8 w */
/*********************************************************************/
/* Start extra pixmap definitions here. One each for A,B,C and the */
/* mask. The arrangement of these is an exact image of the real */
/* registers. (As a result, the padding was included). */
/* Note that these 'shadow' registers are always in memory so */
/* need not be declared as volatile. */
/*********************************************************************/
USHORT OpDim1;
USHORT OpDim2;
USHORT MaskXOffset;
USHORT MaskYOffset;
USHORT SrcXAddr;
USHORT SrcYAddr;
USHORT PatXAddr;
USHORT PatYAddr;
SHORT DstXAddr;
SHORT DstYAddr;
ULONG PixOp;
BYTE bFifthStep; /* used by software simulation only */
BYTE pixmapIndexA;
BYTE bPaddingA;
ULONG pixmapBaseA;
USHORT pixmapWidthA;
USHORT pixmapHeightA;
BYTE pixmapFormatA;
BYTE bPaddingA2;
BYTE pixmapIndexB;
BYTE bPaddingB;
ULONG pixmapBaseB;
USHORT pixmapWidthB;
USHORT pixmapHeightB;
BYTE pixmapFormatB;
BYTE bPaddingB2;
BYTE pixmapIndexC;
BYTE bPaddingC;
ULONG pixmapBaseC;
USHORT pixmapWidthC;
USHORT pixmapHeightC;
USHORT pixmapFormatC;
BYTE bPaddingC2;
BYTE pixmapIndexM;
BYTE bPaddingM;
ULONG pixmapBaseM;
USHORT pixmapWidthM;
USHORT pixmapHeightM;
BYTE pixmapFormatM;
BYTE bPaddingM2;
} MM8514Reg;
typedef MM8514Reg FAR * pMM8514Reg;
The top 3/4 part of this structure corresponds to 8514/A registers. However, immediately after the volatile MISCIO Misc_IO field, notice the definitions of several XGA registers. These have to exist because of the bit-map drawing code in the module named eddf_MESS(). The shadow registers are named Shadow8514Regs in the 8514/A driver. The following is an example of conditionally compiled code:
/**************************************************************/
/* set the foreground and background colors for the blt. */
/* These are taken from the target attribute bundle */
/* unless colour information was passed in the parameters */
/**************************************************************/
#ifndef _8514
if (ArgOptions & BLTMODE_ATTRS_PRES)
{
ShadowXGARegs.FgCol = (USHORT)LogToPhyIndex(ArgAttrs->lColor);
ShadowXGARegs.BgCol = (USHORT)LogToPhyIndex(ArgAttrs->lBackColor);
}
else /* use attribute bundle colours */
{
ShadowXGARegs.FgCol = (USHORT)pdc->DCIImagColatts.ForeColor;
ShadowXGARegs.BgCol = (USHORT)pdc->DCIImagColatts.BackColor;
}
#else
/**************************************************************/
/* set the foreground and background colors for the blt. */
/* These are taken from the target attribute bundle */
/* unless color information was passed in the parameters */
/**************************************************************/
if (ArgOptions & BLTMODE_ATTRS_PRES)
{
Shadow8514Regs.Color_1 = LogToPhyIndex(ArgAttrs->lColor);
Shadow8514Regs.Color_0 = LogToPhyIndex(ArgAttrs->lBackColor);
}
else /* use attribute bundle colours */
{
Shadow8514Regs.Color_1 = pdc->DCIImagColatts.ForeColor;
Shadow8514Regs.Color_0 = pdc->DCIImagColatts.BackColor;
}
#endif
In addition to changing the name of the structure, the fields that corresponded closely between the two devices were renamed to match the 8514/A structure. The 8514/A and XGA support the same binary raster operations, although they are encoded differently. The MESS code understands 8514/A raster operations, except for the line drawing code, which still uses XGA raster operations. The MESS code does not understand 8514/A commands, however. Thus, the 8514/A driver code must set up XGA pixel operations because the MESS code depends on them. Also, parts of the 8514/A hardware-drawing code reads the XGA pel operation that is set up by the higher-level portions of the driver, and also sets appropriate bits in the 8514/A command register. Blt directions for overlapping Bitblts are handled in this manner.
The result of this process is the bit-map drawing code, which should be relatively device-independent, is dependent on both 8514/A and XGA hardware at the same time. The MESS code is dependent on certain fields in the bit-map header that really should be reserved for the hardware-drawing code. In particular, the MESS code assumes that the hw_width field (the width of the bit map in hardware) is one less pel than the width of the bit map. The 8514/A and XGA refer to widths and heights in 0-based units. Therefore, 0 means 1, 1 means 2, and so on. Not all drivers work this way.