Format a task state segment.

Syntax:

────── DT ───────┬─────────┬──────────────────────────────────
                   └─ addr ──┘

Parameters:

addr

The address of the task state segment to be formatted. If not specified then the current TSS pointed to by the TR (task register) is used.

Results & Notes:

The TSS is formatted as follows:

────────────────────────────────────────────────────────────────────────##dt 10:0
eax=00000000 ebx=00000000 ecx=00000000 edx=00000000 esi=00000000 edi=00000000
eip=00000000 esp=00000000 ebp=00000000 iopl=0 -- -- -- nv up di pl nz na po nc
cs=0000 ss=0000 ds=0000 es=0000 fs=0000 gs=0000  cr3=001d1000
ss0=0030  esp0=000066fc  ss1=0000  esp1=00000000  ss2=0866  esp2=00001000
ldtr=0028  link=0000  tflags=0000  i/o map=dfff
ports trapped: 0-ffff
────────────────────────────────────────────────────────────────────────

Each of the fields displayed has the following meaning:

Note:

Some of the TSS fields are set at task creation and other when a task switch occurs.

eax=

Saved EAX register when a task switch occurs.
ebx=
Saved EBX register when a task switch occurs.
ecx=
Saved ECX register when a task switch occurs.
edx=
Saved EDX register when a task switch occurs.
esi=
Saved ESI register when a task switch occurs.
edi=
Saved EDI register when a task switch occurs.
eip=
Saved EIP register when a task switch occurs.
esp=
Saved ESP register when a task switch occurs.
ebp=
Saved EBP register when a task switch occurs.
iopl=
Saved EGLAGS iopl and flag settings when a task switch occurs. See .R command for an explanation of the flag abbreviations.
cs=
Saved CS register when a task switch occurs.
ss=
Saved SS register when a task switch occurs.
ds=
Saved DS register when a task switch occurs.
es=
Saved ES register when a task switch occurs.
fs=
Saved FS register when a task switch occurs.
gs=
Saved GS register when a task switch occurs.
cr3=
CR3 register at task creation.

Note: This provides the real address of the Page Directory Table, which never alters under OS/2.

ss0=
Ring 0 SS register used for ring 0 privilege transitions.
esp0=
Ring 0 ESP register used for ring 0 privilege transitions.
ss1=
Ring 1 SS register used for ring 1 privilege transitions.
esp1=
Ring 1 ESP register used for ring 1 privilege transitions.

Note: Ring 1 is not used under OS/2.

ss2=
Ring 2 SS register used for ring 2 privilege transitions.
esp2=
Ring 1 ESP register used for ring 2 privilege transitions.
ldtr=
LDTR register at task creation.
link=
TR register value of previous nested task's TSS.
tflags=
The debug trap bit for this task.
i/o maps=
Offset to the I/O permission map from the beginning of this TSS.

Note: It is permissible for the i/o map offset to point beyond the TSS segment. This signifies that no I/O permissions are granted and all ports will be trapped.

ports trapped:
List the range of I/O port addresses that will generate traps if accessed by this task.

Notes:

For performance reasons hardware implemented task switching is used only in a limited way in OS/2. TSSs defined by OS/2 include:

Protect mode code (TSS selector 10)

Virtual DOS Machines

Non Maskable Interrupt handling (trap 2, TSS selector 1E38)

Double Fault handling (trap 8, TSS selector 88)

All protect-mode processes run under a common top-level task using selector 10 as the TSS selector.

The seltss (PTDA +0x2f0) field of the PTDA records the top-level task's TSS selector used by a given process, thus may be used to find the TSS selector for Virtual DOS Machines.

Refer to Intel Pentium User's Guide and Intel x86 Programmer's Reference for more information on the Task State Segment and Hardware architected multi-tasking.

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